ReflexScript Compiler

ReflexScript Compiler — Evaluation Only. Copyright © 2026 Mirror AI, Corp. All rights reserved. Proprietary software. By using this tool you agree it may not be used for production, redistributed, or reverse engineered.

Full terms

This WebAssembly build of the ReflexScript Compiler (reflexc) is provided by Mirror AI, Corp. for evaluation purposes only. By accessing or using this software you agree to the following terms:

No production, commercial, or revenue-generating use.
No redistribution, sublicensing, or hosting on third-party sites.
No reverse engineering, disassembly, decompilation, or extraction of the WebAssembly module, beyond what is permitted by applicable law.
No use of the generated output (C, SystemVerilog, reports) in any shipping product without a separate commercial license.
Provided "as is" without warranty of any kind. Not certified for safety-critical use under this evaluation license.

Contact kevin.weekly@mirrorai.dev for a commercial license.

Files

no file

Compile options

Output target C (struct interface) C (flat, legacy) C + Verilog Verilog only (--target hdl)

Pedanticness Strict Permissive (all lints warn) Custom …

ambiguous parens → warn implicit narrowing → warn signed/unsigned mix → warn

Analysis Strict WCET Require safety blocks

Verilog options Fixed-point conversion Fractional bits: Trig LUT size: Debug ports

Diagnostics

License and compiler output will appear here on every run.